Recent years have seen an increase in the number of applications for services of, for example, video on demand type services. Examples of such services include video-conferencing through the Internet, digital video broadcasting, and streaming of video contents. These applications rely on transmission of video information. When video data is transmitted or recorded, a considerable amount of data is transmitted through a conventional transmission path having a limited bandwidth or is stored in a conventional recording medium having a limited data storage capacity. In order to transmit the video information through the conventional transmission channel or store the video information onto the storage medium, it is essential to compress or reduce the amount of digital data.
For the purpose of compressing video data, many video coding standards have been developed. Such video coding standards are, for instance, the International Telecommunication Union Telecommunication Standardization Sector (ITU-T) standards denoted as H.26× and the ISO/IEC standards denoted as MPEG-x. The most advanced video coding standards are currently the standards denoted as H.264/AVC or MPEG-4/AVC (see Non-patent Literature 1 and Non-patent Literature 2).
The data compression processes in the H.264/AVC Standard is roughly divided into prediction, transform, quantization, and entropy coding. The entropy coding is intended to reduce redundant information in information to be used for the prediction and quantized information. Representatives of entropy coding include variable-length coding, adaptive coding, and fixed-length coding. Representatives of variable-length coding include Huffman coding, run-length coding, and arithmetic coding. Among these, arithmetic coding is known as a scheme which is intended to determine output codes by calculating symbol occurrence probabilities and which provides a high coding efficiency by determining codes according to the features of image data, compared to Huffman coding which uses a fixed coding table.
With reference to FIGS. 22 to 24, a conventional arithmetic decoding method is described.
First, a flow of arithmetic decoding is described below with reference to FIGS. 22 to 24.
FIG. 22 is a block diagram of a structure of an arithmetic decoder which performs conventional H.264/AVC arithmetic decoding processes. As shown in FIG. 22, the arithmetic decoder 90 includes a context selection (Context Selection) unit 91, a context load (Context Load) unit 92, a binary arithmetic decoder (Bin Decoder) 93, a de-binarizer (De-Binarizer) 94, a context update (Context Update) unit 95, and context memory (Context Memory) 96.
FIG. 23 is a flowchart of the arithmetic decoding processes.
First, the context selection unit 91 performs a process for selecting a context for each of decoding target signals (Step S01). In the context selection, for example, an already decoded decoding symbol or an already decoded signal of a de-binarized neighboring block is obtained. According to a predetermined method, the context is determined and the determined context number is notified to the context load unit 92.
The context load unit 92 loads a symbol occurrence probability corresponding to the context specified by the context memory 96 according to the context number (Step S02). Based on the loaded symbol occurrence probability, the binary arithmetic decoder 93 performs an arithmetic decoding process (Step S03).
The context update unit 95 performs an update process on the context used for decoding from the decoding symbol resulting from the arithmetic decoding (Step S04). In the context update process, the symbol occurrence probability corresponding to the context is updated, and the updated symbol occurrence probability is stored in the context memory 96. On the other hand, the decoded symbols resulting from the arithmetic decoding are subjected to a de-binarization process (Step S05), and decoded signals obtained from the decoding target signals are output.
FIG. 24 is a schematic diagram of processing timings for parallel processes implemented to perform faster arithmetic decoding processes.
FIG. 24 illustrates, along a time axis, a context selection process (CS), a context load process (CL), a binary arithmetic decoding process (BAD), and a context update (CU) operation in a processing circuit for a process 1 (Proc1). For simplicity, the time periods required for the respective processes and operation are equal in FIG. 24. This example also shows a process 2 (Proc2), a process 3 (Proc3), and a process 4 (Proc4).
Each of parts associated by a corresponding one of the arrows in the diagram has a dependency that they need to be processed in the sequence shown by the arrow. In the binary arithmetic decoding process, a current internal state in binary arithmetic decoding is updated for each decoding. This is why the binary arithmetic decoding process involves such a dependency. In addition, in the case where the same context is used (as in the case shown in the diagram), a result of updating the context is further used for reference, and thus there is a dependency between the context update (CU) and the context load (CL) for next decoding.